Lithography is a process used to create features on the surface of substrates. Such substrates can include those used in the manufacture of flat panel displays, circuit boards, various integrated circuits, and the like. A frequently used substrate for such applications is a semiconductor wafer. One skilled in the relevant art will recognize that the description herein also applies to other types of substrates. In such a case, the patterning device may generate a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single substrate will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time.
In current apparatus, employing, for example, patterning using a mask on a mask table, a distinction can be made between two different types of machine. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire pattern onto the target portion at once; such an apparatus is commonly referred to as a stepper. In a further apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the pattern with respect to the beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (with M<1) the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a pattern (e.g. from a mask) is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming; resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
For the sake of simplicity, the projection system may hereinafter be referred to as the “projection lens”; however, this term should be broadly interpreted as encompassing various types of projection system. Depending on the wavelength of the radiation used in the lithographic apparatus, the projection system may include refractive optics, reflective optics, and catadioptric systems, for example. The illumination and/or projection system may include components operating according to any of these design types for directing, shaping or controlling the beam of radiation, and such components may be referred to below, collectively or singularly, as a “lens”. The wavelength of the radiation used in the lithographic apparatus may be in the UV range, e.g. 365 nm, the DUV range, e.g. 248 or 193 nm or in the EUV range, e.g. 13.5 nm. The position of a second element traversed by the beam relative to a first element traversed by the beam will for simplicity hereinafter be referred to as “downstream” of or “upstream” of the first element. In this context, the expression “downstream” indicates that a displacement from the first element to the second element is a displacement along the direction of propagation of the beam; similarly, “upstream” indicates that a displacement from the first element to the second element is a displacement opposite to the direction of propagation of the beam. Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more patterning device tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Dual stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441 and PCT patent application publication no. WO 98/40791, incorporated herein by reference.
There is a desire, for example, to integrate an ever-increasing number of electronic components in an IC. To realize this it is necessary to decrease the size of the components and therefore to increase the resolution of the projection system, so that increasingly smaller details, or line widths, can be projected on a target portion of the substrate. As the critical dimension (CD), i.e. the dimension of a feature or features, such as the gate width of a transistor, in which variations will cause undesirable variation in physical properties of the feature, in lithography shrinks, consistency of focus, both across a substrate and between substrates, becomes increasingly important. Traditionally, optimal settings were determined by “send-ahead wafers” i.e. substrates that are exposed, developed and measured in advance of a production run. In the send-ahead wafers, test structures were exposed in a so-called focus-energy matrix (FEM) and the best focus and energy settings were determined from examination of those test structures.
U.S. patent application no. U.S. 60/996,506 describes a method of measuring a uniformity of focus of a lithographic projection apparatus. The method includes exposure of a photoresist covered test substrate with a plurality of verification fields. Each of the verification fields includes a plurality of verification marks, and the verification fields are exposed using a certain focus offset FO. After developing, an alignment offset for each of the verification marks is measured and translated into defocus data using a transposed focal curve.
The use of a verification method to monitor focus and energy settings was disclosed in European patent application publication no. EP 1 256 849. The verification method includes imaging a verification mark onto a radiation-sensitive layer. The verification mark includes a grating and has at least a first part and a second part. The apparent imaged position of the first part is predominantly sensitive to the focus setting and the apparent imaged position of the second part is predominantly sensitive to the dose setting. The verification mark is first calibrated by determining the sensitivity of its image for certain dose and focus settings. By subsequently measuring the shifts in apparent position of the first and the second parts in the lithographic apparatus, the relative focus setting and the relative dose setting can be determined, so that the lithographic apparatus can be verified.